As is known in the art, oversampling has become popular in recent years for converting signals between analog and digital formats. Oversampling avoids the difficulties encountered with conventional analog-to-digital and digital-to-analog (ADC, DAC) conversion techniques employing relatively low sampling rates, typically the Nyquist rate of the signal. Conventional analog-to-digital and digital-to-analog techniques require very precise analog components in the filter and conversion circuits because of their vulnerability to noise and interference.
Conversely, oversampling ADC or DAC's are able to use relatively simple high-tolerance components to achieve high resolution. By sampling at much higher frequencies than the Nyquist rate of the signal the difficulties of the conventional analog-to-digital and digital-to-analog techniques are avoided. Oversampling ADC or DAC's permit simple and relatively high-tolerance analog components to achieve high resolution. However, fast and complex digital signal processing techniques are required to implement the filtering of the aliasing frequencies in ADC's.
FIG. 1 is a block diagram of an oversampling Delta/Sigma DAC of the related art. A digital data word 5 indicating an amplitude of a sampled analog signal is applied to an interpolation filter 7. The interpolation filter 7 up-samples the digital data word 5 to produce an approximation of the sequence that would have been obtained by sampling the signal at a higher frequency. The interpolation filter 7 creates a sequence of the digital data word 5 that comprises the original samples separated by zeros. A low pass filter smoothes out the discontinuities to replace the zeros with values that approximate the values of the digital data word 5 had the sampling frequency been an oversampling ratio times the original sampling frequency. The original digital data word 5 consists of a relatively large number of bits e.g. 24 bits determined by the sensitivity or the original analog-to-digital converter. The output of the interpolation filter is transferred to a Delta/Sigma modulator 10. The Delta/Sigma modulator 10 attenuates images due to the interpolation operation and band limits the signal at the output of the Delta/Sigma modulator 10 to the Nyquist frequency. The Delta/Sigma modulator 10 truncates the number of bits representing the signal e.g. to 3 bits to take advantage of both oversampling and noise shaping to keep the signal-to-noise ratio of the output signal of the Delta/Sigma modulator 10 as close as possible to signal-to-noise ratio of the oversampled input. The output of the Delta/Sigma modulator 10 is applied to a dynamic element matching circuit 20. As is known in the art, the differences in the layout design and manufacturing processes causes minor differences in the signal levels of each of the DAC elements 30a, 30b, . . . 30n that causes spectral noise in the output signal. The dynamic element matching circuit 20 employs techniques such as barrel shifting, dithered data weighted averaging, incremental data weighted averaging, bi-directional data weighted averaging, partitioned data weighted averaging, rotated data weighted averaging, randomized data weighted averaging, or pseudo data weighted averaging for the selection of the DAC elements 30a, 30b, . . . 30n, and noise shaping techniques to determine the analog signal 40.
Data weighted averaging is used to apply first order mismatch noise shaping to obviate the negative effects of mismatch errors such as noise and distortion between multiple DAC elements. Data weighted averaging is an element rotation process with objective to provide the long-term average use of each unit element of the DAC elements 30a, 30b, . . . 30n to be identical. The pattern of usage of the DAC elements 30a, 30b, . . . 30n is rotated such that the DAC elements 30a, 30b, . . . 30n are selected sequentially.
A data weighted averaging circuit has a thermometer encoder that converts the data output of the Delta/Sigma modulator 10 to a thermometer code that selects the DAC element 30a, 30b, . . . 30n that are to be summed together by the summation circuit 35 to generate the output analog signal 40. A pointer indicates which DAC element 30a, 30b, . . . 30n that is used as the starting point for the digital to analog conversion. A shifter maps the relationship between the thermometer code and DAC element 30a, 30b, . . . 30n. 
The output of the dynamic element matching circuit 20 is applied to the input to the DAC elements 30a, 30b, . . . 30n. The outputs of the DAC elements 30a, 30b, . . . 30n are applied to the summation circuit 35 to determine the amplitude of the output analog signal 40.
Conventionally, the DAC elements 30a, 30b, . . . 30n are usually one bit binary coded {+1,0}, meaning that each DAC elements 30a, 30b, . . . 30n occupies only two (2) different output signal levels. In maximum precision digital-to-analog conversion, the number of DAC elements 30a, 30b, . . . 30n becomes large and the structure of the summation circuit becomes very complex.
FIG. 2 is a block diagram of the Delta/Sigma DAC system of FIG. 1 illustrating the details of a single bit data weighted averaging circuit 20 of the related art. FIG. 3 is a table for the binary-to-thermometer code conversion of the binary-to-thermometer encoder 50 for a single bit encoding of the related art. The digital input 5 is applied to the Delta/Sigma modulator 10 as described above. The output 15 of the Delta/Sigma modulator 10 is applied to the thermometer encoder 50 of the dynamic element matching circuit 20. Referring to FIG. 3, the output 15 of the Delta/Sigma modulator 10 is a digital code that represented as an unsigned binary code that is used to address a conversion memory or logical circuit that determines each output based upon the unsigned binary code.
The output 55a, 55a, . . . , 55n−1, 55n of the thermometer encoder 50 receives the thermometer code selected based on the unsigned binary code 15 applied to the input of the thermometer encoder 50. For example, if the unsigned binary code 15 is set to the binary equivalent of a 5, the outputs 55a, 55a, . . . , 55n−1, 55n that are d1 through d5 are set to a logical 1 and the remaining outputs d6 through d8 are set to a logical zero. The output 55a, 55a, . . . , 55n−1, 55n of the thermometer encoder 50 is applied to the input of the barrel shifter. The output 15 of the Delta/Sigma modulator 10 is applied to the input of an accumulator 65. The accumulator 65 determines the amount that the output 55a, 55a, . . . , 55n−1, 55n of the thermometer encoder 50 is to be rotated by the barrel shifter 60 to provide the data weighted averaging of the DAC elements 30a, 30b, . . . 30n to minimize the negative effects of mismatch errors due process variations for each of the DAC elements 30a, 30b, . . . 30n. 
U.S. Pat. No. 6,583,742 (Hossack) describes digital-to-analog converter (DAC) system that has multiple weighting elements. Some of the weighting elements have a different nominal weight from other elements. Pairs of elements with the same nominal weight are combined, with each pair of elements having more than two output states. A selection unit is coupled to the elements and an adder is coupled to the selection unit to sum the outputs of the weighted elements. In use, the DAC system receives a digital signal and the selection unit determines the output state of each element combination to provide values of the weighted elements which, when summed, are equivalent to the digital signal. The selection unit also determines the output state of each element in each element combination to minimise errors.
U.S. Pat. No. 7,079,063 (Nguyen, et al.) provides a system for processing digital signals in a data converter. The system includes a thermometer encoder for receiving signed binary data and for providing signed thermometer data. The signed thermometer data includes positive thermometer data and negative thermometer data. The system also includes a shuffler that receives positive input data responsive to the positive thermometer data and receives negative input data responsive to the negative thermometer data. The system also includes a decoder for receiving output data from the shuffler and providing decoded data to an analog output stage.